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Sdram
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Computer memory, where do I start. It should be with the
physics of the devices I suppose, My semiconductor book doesn't
mention RAM at all and Sze had some thing to do with the development
of solid state memory. Memory isn't a device its an IC. Ignoring
the physics of the IC. There is static ram(SRAM), Basically
SRAM allows you to put data into an address and read the data
from that address later, later being before you remove the
power. The SRAM cell is an array of flip flops( four FETs
?).
The basics of RAM and CPU operation are shown in figure
1. the CPU is connected by data and address buses to the RAM.
There are some additional connections, CE which is chip enable
would be set to access a particular RAM chip, WE which is
write enable this would be set according to whether you wanted
to read or write to the chip. So when the CPU wants some thing
from an address, oh lets say 0xh, it makes the chip select
high for that particular chip, the write enable goes high(signalling
a read) and the address 0xh is set high on the address bus.
A short time later the RAM chip puts the contents of 0xh on
the data bus. Simple, well I have ignored bundles of details.
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Figure 1 Simplified schematic of CPU and memory. |
Figure 2 Clock cycles, when data is requested and when it's
returned. |
The time taken from strobing the chip select and the write
enable to the time the data is available to the CPU is the
address access time, so an access time of 80 ns means 12.5
MHz(slooow). As I said SRAM memory cells are basically four
FETs Well along came the DRAM cell which is a FET and a capacitor,
so DRAMs are much more compact. This results in memory with
greater memory-density and speed, but Drams don't hold their
data for long so must be accessed or refreshed every so often
(I think this is in the order of 10s of ms).
SDRAM is synchronous dynamic random access memory. Well synchronous
means at the same time? The chipset and the RAM run on a common
clock. Figure 2 is a timing diagram for a CAS 2 SDRAM, PC100
running at 100 MHz, receiving a 100 MHz signal to a pin on
the dimm in time with the 100 MHz signal to the chipset. So
when does the CPU ask for and get the data. The request is
made before the rising edge of the clock, all signals obviously
persist and in this case the "envelope" must encompass the
rising edge as in figure 2. The data is then put on the bus
but again the timing is important, the data must be on the
bus synchronously with the clock and in figure 2 it is 2 rising
edges after the request. This is what Column Address Strobe(CAS)
latency is all about, data out two rising edges after the
request comes in is CAS 2. As there is CAS there must also
be RAS(row address strobe). The CAS latency rating can be
played with i.e. if you want to run your pc100 at 133 MHz
and it proves unstable, run it at CAS 3 and it will be OK(probably).
ECC: I always forget what acronyms mean, Error correction
? Well I can remember what happens so here goes. Parity checking
was used with some memory, this meant slapping another bit
on a byte and if the byte was even sticking a 0 in the parity
check bit, or if the byte was odd sticking a 1 in it; then
checks were made that the 9 bit byte was even(there was also
odd parity checking) if not an error had occurred. ECC uses
code to add a byte of error checking and when an error occurs(shouldn't
happen all that often) corrects it. ECC must therefore stand
for error correction code, I had to work out some error probability
stuff in statistics years ago all I remember was they don't
happen a lot and I wouldn't worry if my SDRAMs weren't ECC.
Unbuffered well I will write that later this page is getting
a bit long.
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